The disclosed embodiments of the present invention relate to Viterbi decoding, and more particularly, to a Viterbi decoding apparatus using a level information generator which supports different hardware configurations to generate required level information to a Viterbi decoder and related method thereof.
Generally speaking, a binarization process is necessary for converting an analog signal to a digital signal for further processing. Among various binarization apparatuses, the Viterbi decoder is known to be able to obtain the least erroneous binary signals. In general, the Viterbi decoder detects optimal binary data based on a statistical characteristic of an input signal. Specifically, the Viterbi decoder detects binary data having fewer errors as optimal binary data of an input signal by using a plurality of levels. For example, the branch metric calculation of the Viterbi decoder may be implemented to subtract a level from the received symbol of the input signal and derive a branch metric from the subtraction result. Therefore, the levels defined by the level information may affect the decoding performance of the Viterbi decoder. If the levels are not properly defined, the reading capability of an electronic device/system using the Viterbi decoder would be degraded. Thus, there is a need for an innovative level information generation design which is capable of providing optimized setting of the levels to the Viterbi decoder for improving the reading capability of the electronic device/system using the Viterbi decoder.